Backside coupling with superconducting partial tsv for transmon qubits

ABSTRACT

A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

TECHNICAL FIELD

The present invention relates generally to a semiconductor device, afabrication method, and fabrication system for coupling readoutcircuitry with superconducting quantum logic circuits. Moreparticularly, the present invention relates to a device, method, andsystem for backside coupling with superconducting partial TSV (ThroughSilicon Via) for transmon qubits.

BACKGROUND

Hereinafter, a “Q” or “q” prefix in a word or phrase is indicative of areference of that word or phrase in a quantum computing context unlessexpressly distinguished where used.

Molecules and subatomic particles follow the laws of quantum mechanics,a branch of physics that explores how the physical world works at themost fundamental levels. At this level, particles behave in strangeways, taking on more than one state at the same time, and interactingwith other particles that are very far away. Quantum computing harnessesthese quantum phenomena to process information.

The computers we use today are known as classical computers (alsoreferred to herein as “conventional” computers or conventional nodes, or“CN”). A conventional computer uses a conventional processor fabricatedusing semiconductor materials and technology, a semiconductor memory,and a magnetic or solid-state storage device, in what is known as a VonNeumann architecture. Particularly, the processors in conventionalcomputers are binary processors, i.e., operating on binary datarepresented in 1 and 0.

A quantum processor (q-processor) uses the odd nature of entangled qubitdevices (compactly referred to herein as “qubit,” plural “qubits) toperform computational tasks. In the particular realms where quantummechanics operates, particles of matter can exist in multiplestates—such as an “on” state, an “off” state, and both “on” and “off”states simultaneously. Where binary computing using semiconductorprocessors is limited to using just the on and off states (equivalent to1 and 0 in binary code), a quantum processor harnesses these quantumstates of matter to output signals that are usable in data computing.

Conventional computers encode information in bits. Each bit can take thevalue of 1 or 0. These 1s and 0s act as on/off switches that ultimatelydrive computer functions. Quantum computers, on the other hand, arebased on qubits, which operate according to two key principles ofquantum physics: superposition and entanglement. Superposition meansthat each qubit can represent both a 1 and a 0 at the same time.Entanglement means that qubits in a superposition can be correlated witheach other in a non-classical way; that is, the state of one (whether itis a 1 or a 0 or both) can depend on the state of another, and thatthere is more information that can be ascertained about the two qubitswhen they are entangled than when they are treated individually.

Using these two principles, qubits operate as more sophisticatedprocessors of information, enabling quantum computers to function inways that allow them to solve difficult problems that are intractableusing conventional computers. IBM has successfully constructed anddemonstrated the operability of a quantum processor (IBM is a registeredtrademark of International Business Machines corporation in the UnitedStates and in other countries.)

A superconducting qubit may include a Josephson junction. A Josephsonjunction is formed by separating two thin-film superconducting metallayers by a non-superconducting material. When the metal in thesuperconducting layers is caused to become superconducting—e.g. byreducing the temperature of the metal to a specified cryogenictemperature—pairs of electrons can tunnel from one superconducting layerthrough the non-superconducting layer to the other superconductinglayer. In a superconducting qubit, the Josephson junction—which has aninductance—is electrically coupled in parallel with one or morecapacitive devices forming a nonlinear resonator.

The information processed by qubits is emitted in the form of microwaveenergy in a range of microwave frequencies. The microwave emissions arecaptured, processed, and analyzed to decipher the quantum informationencoded therein. For quantum computing of qubits to be reliable, quantumcircuits, e.g., the qubits themselves, the readout circuitry associatedwith the qubits, and other types of superconducting quantum logiccircuits, must not alter the energy states of the particles or themicrowave emissions in any significant manner. This operationalconstraint on any circuit that operates with quantum informationnecessitates special considerations in fabricating semiconductor and/orsuperconductor structures that are used in such a circuit.

The readout circuitry is generally coupled with a qubit byelectromagnetic resonance (usually a microwave or radio-frequencyresonance) using a resonator. A resonator in the readout circuitrycomprises inductive and capacitive elements. The illustrativeembodiments recognize that a superconducting capacitive coupling usedwith a superconducting quantum logic circuit, and particularly to couplea readout circuit with a qubit is significantly larger in size than thesize of the Josephson junction therein. FIG. 1 depicts a scaled image ofqubit with a presently fabricated capacitive coupling to externalcircuits. Image 100 shows a portion of a qubit chip. Coupling capacitors102 couple with transmission lines (not visible) that bring theelectromagnetic signal out from Josephson junction 104. Capacitor pads106 are capacitive devices driving Josephson junction 104 and forming anonlinear resonator. A ground-plane (not visible) typically surroundsall or a portion of this structure.

As can be seen, fabricating capacitive coupling structures 102 in acoplanar manner with the structures of qubit 100 takes up the verylimited planar real-estate on the fabrication plane of chip 100.Josephson junction 104—which is barely visible in the image of thisfigure—occupies only a fraction of the exaggerated box drawn around thejunction to identify its position. The area occupied by capacitivecoupling structures 102 is significantly more than the area of Josephsonjunction 104.

A capacitive coupling structure as in any one of the capacitive couplingstructures 102, is fabricated coplanar with the qubit elements such asthe Josephson junction and the junction's driving capacitors. Theillustrative embodiments recognize that fabricating capacitive couplingdevices as coplanar to the qubit circuit elements limits the number ofqubits that can be fabricated per die in a fabrication process. Theillustrative embodiments recognize that a need exists for a method offabricating a capacitive coupling device that is not in the same planeof fabrication as the Josephson junction or its driving capacitors.

A capacitive coupling structure that can be used in place of any one ofthe capacitive coupling structures 102, is interchangeably referred toherein as C-coupler. A superconducting C-coupler according to anillustrative embodiment is not coplanar with the qubit elements. A planeof a fabrication substrate, e.g., a silicon substrate of asemiconducting wafer, on which the superconducting qubit elements arefabricated is referred to herein as a “front” side (front, frontside)regardless of the actual orientation of the plane during fabrication. A“back” side (back, backside) of the substrate is opposite the frontside,to wit, an opposite surface of the same wafer which is substantiallyparallel to the front side of the wafer.

The structures of a superconducting C-coupler are fabricated from thebackside, through the substrate, in a substantially perpendiculardirection from the frontside plane of fabrication of the qubit. Astructure that is formed through a silicon substrate in a directionperpendicular to a plane of fabrication is referred to as a“Through-Silicon via” or “TSV” or simply a “via”. Normally, a via passescompletely through the silicon substrate from one side—e.g. thefrontside—to the other side—e.g., the backside. A structure of thesuperconducting C-coupler protrudes partially through the thickness ofthe substrate between the frontside and the backside. Such a structureis referred to herein as a “partial via”.

This manner of fabricating a superconducting C-coupler allows thecapacitive coupling to be removed from the fabrication plane of thequbit, freeing up space in that plane for more qubit elements but stillenabling the capacitive coupling between qubit elements and a readoutcircuit. Additionally, the partial vias of the superconducting C-couplerallow the readout circuitry to also be desirably placed or fabricated onthe back side.

SUMMARY

The illustrative embodiments provide a superconducting device, and amethod and system of fabrication therefor. A superconducting device ofan embodiment comprises a capacitive coupling device (superconductingC-coupler), the embodiment including a trench through a substrate, froma backside of the substrate, reaching a depth in the substrate,substantially orthogonal to a plane of fabrication on a frontside of thesubstrate, the depth being less than a thickness of the substrate. Theembodiment includes a superconducting material deposited as a via layerin the trench with a space between surfaces of the via layer in thetrench remaining accessible from the backside. The embodiment includes asuperconducting pad on the frontside, the superconducting pad couplingwith a quantum logic circuit element fabricated on the frontside. Theembodiment includes an extension of the via layer on the backside,wherein the extension couples to a quantum readout circuit elementfabricated on the backside. Thus, the embodiment provides a non-coplanarcapacitive coupling partial via that saves space in the fabricationplane of a qubit device for other purposes, such as for additional qubitdevices.

Another embodiment further includes a dielectric material filled, fromthe backside, in the space between the surfaces of the via layer. Thus,the embodiment provides one specific manner of forming the partial via.

In one embodiment, the dielectric material is Silicon oxide (SiO2).Thus, the embodiment provides a specific material for forming onestructure of the partial via.

In another embodiment, the dielectric material is etched such that thedielectric material is removed and the space is occupied by air. Thus,the embodiment provides a process by which another material can be usedfor forming one structure of the partial via.

In another embodiment, a layer of a second superconducting material isdeposited on the frontside, and wherein the layer of the secondsuperconducting material is masked and etched to form thesuperconducting pad on the frontside. Thus, the embodiment provides astructure and a method of forming said structure to capacitively couplewith the partial via.

In another embodiment, the layer of the second superconducting materialis deposited prior to forming the trench, and wherein the layer of thesecond superconducting material is protected by a sacrificial layer.Thus, the embodiment provides one sequence of fabrication operationswhich forms the structure to capacitively couple with the partial via.

In another embodiment, the extension of the via layer is electricallycoupled with the quantum readout circuit element. Thus, the embodimentprovides one structure using which the partial via can be used in areadout circuit.

In another embodiment, the extension of the via layer is directlyelectrically coupled with the quantum readout circuit element. Thus, theembodiment provides one method of coupling the partial via with thereadout circuit.

In another embodiment, the extension of the via layer is electricallycoupled to a second superconducting pad on the backside, and wherein thesecond superconducting pad couples with the quantum readout circuitelement. Thus, the embodiment provides another method of coupling thepartial via with the readout circuit.

In another embodiment, an additional set of partial trenches containingsuperconducting via layers is included in the device, with thesesuperconducting via layers electrically connected to a ground-plane onthe back side of the substrate. These additional vias are positioned toprovide a grounding shield between C-couplers vias, to reducecross-coupling among nearby C-couplers. The additional vias arefabricated simultaneously and identically to the superconductingC-coupler vias.

An embodiment includes a fabrication method for fabricating thesuperconducting device.

An embodiment includes a fabrication system for fabricating thesuperconducting device.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features of the invention are set forth in the appendedclaims. The invention itself, however, as well as a preferred mode ofuse, further objectives and advantages thereof, will best be understoodby reference to the following detailed description of the illustrativeembodiments when read in conjunction with the accompanying drawings,wherein:

FIG. 1 depicts a block diagram of another example step in the firstexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 2 depicts a schematic of a superconducting C-coupler used tocapacitively couple with a superconducting element of a quantum logiccircuit in accordance with an illustrative embodiment;

FIG. 3 depicts another schematic of a superconducting C-coupler used tocapacitively couple with a superconducting element of a quantum logiccircuit in accordance with an illustrative embodiment;

FIG. 4 depicts a block diagram of an example step in the first examplefabrication process for fabricating a superconducting C-coupler inaccordance with an illustrative embodiment;

FIG. 5 depicts a block diagram of another example step in the firstexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 6 depicts a block diagram of another example step in the firstexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 7 depicts a block diagram of an example step in the first examplefabrication process for fabricating a superconducting C-coupler inaccordance with an illustrative embodiment;

FIG. 8 depicts a block diagram of another example step in the firstexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 9 depicts a block diagram of another example step in the firstexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 10 depicts a block diagram of another example step in the firstexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 11 depicts a block diagram of another example step in the firstexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 12 depicts a block diagram of another example step in the firstexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 13 depicts a block diagram of an example step in the second examplefabrication process for fabricating a superconducting C-coupler inaccordance with an illustrative embodiment;

FIG. 14 depicts a block diagram of another example step in the secondexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 15 depicts a block diagram of another example step in the secondexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 16 depicts a block diagram of another example step in the secondexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 17 depicts a block diagram of an example step in the second examplefabrication process for fabricating a superconducting C-coupler inaccordance with an illustrative embodiment;

FIG. 18 depicts a block diagram of another example step in the secondexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 19 depicts a block diagram of another example step in the secondexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 20 depicts a block diagram of another example step in the secondexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment;

FIG. 21 depicts a block diagram of another example step in the secondexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment; and

FIG. 22 depicts a block diagram of another example step in the secondexample fabrication process for fabricating a superconducting C-couplerin accordance with an illustrative embodiment.

DETAILED DESCRIPTION

The illustrative embodiments used to describe the invention generallyaddress and solve the above-described need for superconductingC-coupler. The illustrative embodiments provide a fabrication method forbackside coupling with superconducting partial TSV for transmon qubits.

An embodiment can be implemented as a superconducting capacitive devicefor capacitive coupling with a superconducting quantum logic circuit,including but not limited to as a superconducting C-coupler coupled to asuperconducting qubit, in a qubit chip. A fabrication method forsuperconducting C-couplers can be implemented as a software application.The application implementing an embodiment can be configured to operatein conjunction with an existing semiconductor/superconductor fabricationsystem—such as a lithography system.

For the clarity of the description, and without implying any limitationthereto, the illustrative embodiments are described using a simplifieddiagram of the example superconducting C-coupler in the figures and theillustrative embodiments. In an actual fabrication of a superconductingC-coupler, additional structures that are not shown or described herein,or structures different from those shown and described herein, may bepresent without departing the scope of the illustrative embodiments.Similarly, within the scope of the illustrative embodiments, a shown ordescribed structure in the example superconducting C-coupler may befabricated differently to yield a similar operation or result asdescribed herein.

Differently shaded portions in the two-dimensional drawing of theexample structures, layers, and formations are intended to representdifferent structures, layers, materials, and formations in the examplefabrication, as described herein. The different structures, layers,materials, and formations may be fabricated using suitable materialsthat are known to those of ordinary skill in the art.

A specific shape, location, position, or dimension of a shape depictedherein is not intended to be limiting on the illustrative embodimentsunless such a characteristic is expressly described as a feature of anembodiment. The shape, location, position, dimension, or somecombination thereof, are chosen only for the clarity of the drawings andthe description and may have been exaggerated, minimized, or otherwisechanged from actual shape, location, position, or dimension that mightbe used in actual photolithography to achieve an objective according tothe illustrative embodiments.

An embodiment when implemented in an application causes a fabricationprocess to perform certain steps as described herein. The steps of thefabrication process are depicted in the several figures. Not all stepsmay be necessary in a particular fabrication process. Some fabricationprocesses may implement the steps in different order, combine certainsteps, remove or replace certain steps, or perform some combination ofthese and other manipulations of steps, without departing the scope ofthe illustrative embodiments.

The illustrative embodiments are described with respect to certain typesof materials, electrical properties, structures, formations, layersorientations, directions, steps, operations, planes, dimensions,numerosity, data processing systems, environments, components, andapplications only as examples. Any specific manifestations of these andother similar artifacts are not intended to be limiting to theinvention. Any suitable manifestation of these and other similarartifacts can be selected within the scope of the illustrativeembodiments.

The illustrative embodiments are described using specific designs,architectures, layouts, schematics, and tools only as examples and arenot limiting to the illustrative embodiments. The illustrativeembodiments may be used in conjunction with other comparable orsimilarly purposed designs, architectures, layouts, schematics, andtools.

The examples in this disclosure are used only for the clarity of thedescription and are not limiting to the illustrative embodiments. Anyadvantages listed herein are only examples and are not intended to belimiting to the illustrative embodiments. Additional or differentadvantages may be realized by specific illustrative embodiments.Furthermore, a particular illustrative embodiment may have some, all, ornone of the advantages listed above.

A qubit is only used as a non-limiting example superconducting quantumlogic circuit in which an embodiment can be used. From this disclosure,those of ordinary skill in the art will be able to conceive many othersuperconducting quantum logic circuits in which the verticalq-capacitors of the illustrative embodiments will be usable, and thesame are contemplated within the scope of the illustrative embodiments.

With reference to FIG. 2, this figure depicts a schematic of asuperconducting C-coupler used to capacitively couple with asuperconducting element of a quantum logic circuit in accordance with anillustrative embodiment. In schematic configuration 200, superconductingC-coupler 202 represents a q-capacitor fabricated in a manner describedherein, e.g., usable in place of coupling capacitors 102 in FIG. 1.

Substrate 201 is formed of a suitable substrate material, such as, butnot limited to, Silicon (Si). Substrate has a frontside and a backsideas shown. Superconducting C-coupler 202 is formed partially throughsubstrate 201 as shown. Superconducting C-coupler 202 comprises partialvias 208 which are formed from the backside, in a directionsubstantially perpendicular to the plane of fabrication of the quantumlogic circuit, to wit, the frontside, but not quite reaching thefrontside. A thickness “d” of substrate 201 remains between top 208A ofpartial vias 208 and the bottom of capacitive pads 206. In one exampleembodiment, d is of the order of 10-100 microns. Capacitive pads 206 arequbit elements similar to capacitor pads 106 in FIG. 1.

Top 208A of a partial via 208 and a capacitive pad 206 together formcapacitive coupling 204. The substrate remaining in thickness d, e.g.,Si of thickness d, forms dielectric 205 in capacitive coupling 204. Inone embodiment, entire partial via 208 and capacitive pad 206 formscapacitive coupling 204.

In an additional embodiment, some of the partial vias 208 may begrounded on the back-side of the wafer in order to form a shield betweenq-capacitor vias. The grounded partial vias connect to a ground-planeintegrated within the resonators and I/O pads 210 on the back-side ofthe wafer. This ground shield serves the same function as theground-plane that exists in typical coplanar circuits (FIG. 1), andreduces cross-coupling among nearby q-capacitor vias.

Partial via 208 comprises a trench that is lined with a superconductingmaterial (SC2). The superconducting material (SC1) of the capacitivepads 206 and SC2 can be different but need not be different. Forexample, SC1 may be Niobium (Nb) because Nb is conducive to sputteringmethod of deposition, and SC2 may be Titanium nitride (TiN) because TiNis more suitable for atomic layer deposition (ALD).

The trench lining of partial via 208 comprises top portion 208A of thelining and side layer portions 208B of the lining. Additionally, in someembodiments, the lining may extend onto the backside surface in the formof pads 210. Pads 210 are usable to couple with a readout circuitcomponent, e.g., a resonator or an input/output device/line.

In this example depiction, a space inside the SC2 lining in the trenchof partial via 208 is shown filled with filler 203. In one example,filler 203 is an oxide, e.g., Silicon-oxide (SiO2). In anotherembodiment, filler 203 is air, vacuum of a certain degree, or anothersuitable insulating material.

With reference to FIG. 3, this figure depicts another schematic of asuperconducting C-coupler used to capacitively couple with asuperconducting element of a quantum logic circuit in accordance with anillustrative embodiment. In schematic configuration 300, superconductingC-coupler 302 represents a q-capacitor fabricated in a manner describedherein, e.g., usable in place of coupling capacitors 102 in FIG. 1.Configuration 300 includes some features that are similar to thosedescribed in configuration 200 of FIG. 2. All reference numerals thatare common between FIG. 2 and FIG. 3 represent the features as describedwith respect to FIG. 2.

Partial via 208 may extend on the backside in a variety of ways. Oneexample non-limiting manner of extending the superconducting lining ofthe trench of partial via 208 was depicted in FIG. 2. FIG. 3 showsanother non-limiting manner of extending the superconducting lining ofthe trench of partial via 208 on the backside of substrate 201. Here,one side portion 208B of the lining of a partial via 208 includesextension 304 on the backside. The other side portion 208B of the liningin the same partial via 208 terminates at the surface of the backside.Extension 304 connects with superconducting pad 310. Superconducting pad310 can be formed using SC1 of pads 206 or another material differentfrom SC2 of the lining of partial vias 208. Pad 310 is then usable tocouple with a readout circuit component, e.g., a resonator, aninput/output device/line, or a ground-plane integrated within theresonators and I/O pads 310. In this way some of the partial vias 208may serve as a ground shield between nearby q-capacitor vias.

Additionally, partial vias 208 are depicted as hollow and open. In otherwords, where oxide 203 was used as the filler in partial vias 208 inconfiguration 200, configuration 300 depicts partial vias 208 filledwith filler 303, which is air, vacuum or partial vacuum, or anothersuitable insulating material.

Note that fabrication of the lining of partial vias 208 in the manner ofconfigurations 200 and 300 and the nature of filler 203 and 303,respectively therein, are not dependent upon one another. Configuration200 can be fabricated with air filler and configuration 200 can befabricated with oxide filler within the scope of the illustrativeembodiments.

Capacitive coupling 204 is communicating the qubit information to thereadout circuitry through partial vias 208. Each partial via 208comprises a continuous conducting structure. The enclosed area 203 ofeach partial via 208 does not capacitively interfere with its respectivecapacitive coupling 204.

FIGS. 4-12 depict various example steps of one example fabricationprocess for fabricating a superconducting C-coupler. FIGS. 13-22 depictvarious example steps of a second example fabrication process forfabricating a superconducting C-coupler. The superconducting C-couplersformed by the two example processes are structurally different asdescribed below but are functionally equivalent to be interchangeablyusable instead of coupling capacitors 102 in FIG. 1.

With reference to FIG. 4, this figure depicts a block diagram of anexample step in the first example fabrication process for fabricating asuperconducting C-coupler in accordance with an illustrative embodiment.Substrate 201 is the same as described with respect to FIGS. 2-3.

In step 400, layer 402 of superconducting material SC1 is deposited onthe frontside of substrate 201. As a non-limiting example, Nb issputter-deposited on the frontside to form layer 402. Other materialshaving similar superconducting and deposition characteristics as SC1,e.g., for use as pads 206, may be used and suitably deposited as layer402 within the scope of the illustrative embodiments.

With reference to FIG. 5, this figure depicts a block diagram of anotherexample step in the first example fabrication process for fabricating asuperconducting C-coupler in accordance with an illustrative embodiment.Fabrication continues on the frontside of substrate 201.

In step 500, layer 502 of oxide or other similarly protective materialis deposited on superconducting layer 402. As a non-limiting example,SiO2 may be used in layer 502.

With reference to FIG. 6, this figure depicts a block diagram of anotherexample step in the first example fabrication process for fabricating asuperconducting C-coupler in accordance with an illustrative embodiment.Fabrication step 600 continues on the backside of substrate 201.

In fabrication systems that fabricate from only one side, the wafer isturned over such that the fabrication can proceed on the backside. Ascan be seen in this figure, the wafer of substrate 201 has been flippedto bring the backside up, assuming the fabrication system fabricatesfrom the top. In some fabrication systems the flipping of the wafer maybe omitted if the backside can be fabricated without the flip.

One or more trench 602 is formed using a suitable deep trenching method.Reactive ion etching or Bosch etching are examples of deep trenchingmethods that can be used to form trenches 602. In one embodiment, trench602 is formed with an aspect ratio of 20:1, i.e., for every 20 micronsin depth of trench 602, opening 602D of trench 602 expands by 1 micron,giving trench 602 the tapered shape. Essentially, walls 602A and 602B oftrench 602 are substantially parallel within a tolerance defined by thisor similar aspect ratio. In subsequent steps, surface 602C of trench 602will form top 208A as shown in configurations 200 and 300.

With reference to FIG. 7, this figure depicts a block diagram of anexample step in the first example fabrication process for fabricating asuperconducting C-coupler in accordance with an illustrative embodiment.Fabrication continues on the backside of substrate 201.

In step 700, layer 702 of superconducting material SC2 is deposited onthe backside of substrate 201. Layer 702 comprises portions 702A, 702B,702C, and 702D. One or more instances of portions 702A, 702B, 702C, and702D may be present depending upon the number of trenches 602.

Portions 702A, 702B, 702C of layer 702 cover surfaces 602A, 602B, and602C, respectively, of each trench 602. Additionally, portion 702D oflayer 702 covers an untrenched area adjacent to trench 602 on thebackside of substrate 201. Portion 702D will form either pad 210 ofconfiguration 200 or extension 304 of configuration 300 as describedherein. As a non-limiting example, TiN is deposited using ALD on thebackside to form layer 702. Other materials having similarsuperconducting and deposition characteristics may be used and suitablydeposited as material SC2 of layer 702 within the scope of theillustrative embodiments.

With reference to FIG. 8, this figure depicts a block diagram of anotherexample step in the first example fabrication process for fabricating asuperconducting C-coupler in accordance with an illustrative embodiment.Fabrication continues on the backside of substrate 201.

In step 800, layer 802 of oxide or other similarly insulating materialis deposited on superconducting layer 702. The material used to formlayer 802 also forms filler 803, which fills a space remaining insidetrench 602 that is lined with layer 702. As a non-limiting example, SiO2may be used in layer 802. At least some portions of layer 802—e.g., aportion other than portion 803—serves as a protective layer to protect aportion of layer 702 underneath, and is sacrificial in another step ofthe fabrication process.

With reference to FIG. 9, this figure depicts a block diagram of anotherexample step in the first example fabrication process for fabricating asuperconducting C-coupler in accordance with an illustrative embodiment.Fabrication continues on the backside of substrate 201.

In step 900, one or more portions of layer 802 other than filler portion803 are removed to reveal layer 702. For example, a portion of layer 802that overlies portion 702D of layer 702 is removed in this step toreveal portion 702D. The removal process stops at layer 702. ChemicalMechanical Planarization (CMP) is an example removal method that can beused to remove a portion of layer 802.

With reference to FIG. 10, this figure depicts a block diagram ofanother example step in the first example fabrication process forfabricating a superconducting C-coupler in accordance with anillustrative embodiment. Fabrication continues on the backside ofsubstrate 201.

In step 1000, one or more sub-portions of portion(s) 702D are removed.The removal process of this step masks and etches certain sub-portionswhich result in one or more etched areas 1002 and pads 210 forming fromlayer 702D. The masking and etching process of step 1000 can beimplemented using an existing lithography system. This step enables thesuperconducting partial vias to attach to resonators and I/O pads on theback-side of the wafer, or in some embodiments for a subset of thesuperconducting partial vias to connect to resonators and I/O pads whileanother subset of them connects to a ground-plane on the back-side ofthe wafer.

With reference to FIG. 11, this figure depicts a block diagram ofanother example step in the first example fabrication process forfabricating a superconducting C-coupler in accordance with anillustrative embodiment. Fabrication step 1100 continues on thefrontside of substrate 201.

In fabrication systems that fabricate from only one side, the wafer isturned over such that the fabrication can proceed on the frontsideagain. As can be seen in this figure, the wafer of substrate 201 hasbeen flipped to bring the frontside up, assuming the fabrication systemfabricates from the top. If the wafer was not flipped over in step 600,then step 1100 may proceed on the frontside without the flip.

Oxide layer 502, which was protecting superconducting layer 402 isetched, e.g. using a buffered oxide etch if the material of layer 502was silicon oxide. The removal of layer 502 exposes layer 402 as shown.

With reference to FIG. 12, this figure depicts a block diagram ofanother example step in the first example fabrication process forfabricating a superconducting C-coupler in accordance with anillustrative embodiment. Fabrication continues on the frontside ofsubstrate 201.

In step 1200, one or more portions of layer 402 are removed. The removalprocess of this step masks and etches certain portions, which result inone or more etched areas 1202 and pads 206 forming from layer 402.Recall from configuration 200 (or 300) that pads 206 are used aselements of a qubit, e.g., to which a Josephson junction can be coupledor which become parts of a capacitor that drives the Josephson junction.The masking and etching process of step 1200 can be implemented using anexisting lithography system. As can be seen, capacitive coupling 204 isnow formed using top 208A or the entirety of partial vias 208 and a pad206 with intervening dielectric 205 of thickness “d”.

FIGS. 13-22 depict various example steps of a second example fabricationprocess for fabricating a superconducting C-coupler.

With reference to FIG. 13, this figure depicts a block diagram of anexample step in the second example fabrication process for fabricating asuperconducting C-coupler in accordance with an illustrative embodiment.Substrate 201 is the same as described with respect to FIGS. 2-3.

Steps 400 and 500 are performed on substrate 201, as described withrespect to FIGS. 4 and 5.

Again, the wafer is flipped over in a single direction fabricationsystem as in FIG. 6. Essentially, fabrication on the backside is enabledfor the fabrication system by making the backside accessible forfabrication.

In step 1300, layer 1302 of a superconducting material is deposited onthe backside. The superconducting material of layer 1302 can be but neednot be the same as the superconducting material of layer 402. Assuming,as a non-limiting example, that SC1 (Nb) is used for both layers 402 and1302, Nb is sputter-deposited on the backside to form layer 1302. Othermaterials having similar superconducting and deposition characteristicsas SC1 may be used and suitably deposited as layer 1302 within the scopeof the illustrative embodiments.

With reference to FIG. 14, this figure depicts a block diagram ofanother example step in the second example fabrication process forfabricating a superconducting C-coupler in accordance with anillustrative embodiment. Fabrication continues on the backside ofsubstrate 201.

In step 1400, one or more portions of layer 1302 are removed. Theremoval process of this step masks and etches certain portions, whichresult in one or more etched areas 1402 and pads 310 forming from layer1302. Recall from configuration 300 that pads 310 are used to coupleextension 304 of a partial via of a superconducting C-coupler and anexternal circuit, which may comprise resonators, I/O pads andground-planes. The masking and etching process of step 1400 can beimplemented using an existing lithography system.

With reference to FIG. 15, this figure depicts a block diagram ofanother example step in the second example fabrication process forfabricating a superconducting C-coupler in accordance with anillustrative embodiment. Fabrication continues on the backside ofsubstrate 201.

In step 1500, layer 1502 of oxide or other similarly protective materialis deposited on pads 310. As a non-limiting example, SiO2 may be used inlayer 1502. Layer 1502 is a protective sacrificial layer. Layer 1502covers and protects at least pad 310 and can also cover an area ofsubstrate 201 that is exposed around pad 310.

With reference to FIG. 16, this figure depicts a block diagram ofanother example step in the second example fabrication process forfabricating a superconducting C-coupler in accordance with anillustrative embodiment. Fabrication continues on the backside ofsubstrate 201.

In step 1600, one or more trench 1602 is formed using a suitable deeptrenching method in a manner similar to the manner of forming trench 602in FIG. 6. Trench 1602 has characteristics similar to trench 602 withone additional feature. Trench 1602 is formed in such a manner that pad310 is exposed through a wall of trench 1602 (e.g., wall 1602A in caseof one example trench 1602 as shown, or wall 1602B in case of the otherexample trench as shown). Reactive ion etching or Bosch etching areexamples of deep trenching methods that can be used to form trenches1602.

In one embodiment, trench 1602 is formed with an aspect ratio of 20:1,i.e., for every 20 microns in depth of trench 1602, opening 1602D oftrench 1602 expands by 1 micron, giving trench 1602 the tapered shape.Essentially, walls 1602A and 1602B of trench 1602 are substantiallyparallel within a tolerance defined by this or similar aspect ratio. Insubsequent steps, surface 1602C of trench 1602 will form top 208A asshown in configurations 200 and 300.

With reference to FIG. 17, this figure depicts a block diagram of anexample step in the second example fabrication process for fabricating asuperconducting C-coupler in accordance with an illustrative embodiment.Fabrication continues on the backside of substrate 201.

In step 1700, layer 1702 of superconducting material SC2 is deposited onthe exposed surfaces on the backside. Layer 1702 comprises portions1702A, 1702B, 1702C, and 1702D. One or more instances of portions 1702A,1702B, 1702C, and 1702D may be present depending upon the number oftrenches 1602.

Portions 1702A, 1702B, 1702C of layer 1702 cover surfaces 1602A, 1602B,and 1602C, respectively, of each trench 1602. Additionally, portion1702D of layer 1702 establishes an electrical connection with pad 310 asshown. Portion 1702D will form extension 304 of configuration 300 asdescribed herein. As a non-limiting example, TiN is deposited using ALDon the backside to form layer 1702. Other materials having similarsuperconducting and deposition characteristics may be used and suitablydeposited as material SC2 of layer 1702 within the scope of theillustrative embodiments.

With reference to FIG. 18, this figure depicts a block diagram ofanother example step in the second example fabrication process forfabricating a superconducting C-coupler in accordance with anillustrative embodiment. Fabrication continues on the backside ofsubstrate 201.

In step 1800, layer 1802 of oxide or other similarly insulating materialis deposited on superconducting layer 1702. The material used to formlayer 1802 also forms filler 1803, which fills a space remaining insidetrench 1602 that is lined with layer 1702. As a non-limiting example,SiO2 may be used in layer 1802. At least some portions of layer1802—e.g., a portion other than portion 1803—serves as a protectivelayer to protect a portion of layer 1702 underneath, and is sacrificialin another step of the fabrication process.

With reference to FIG. 19, this figure depicts a block diagram ofanother example step in the second example fabrication process forfabricating a superconducting C-coupler in accordance with anillustrative embodiment. Fabrication continues on the backside ofsubstrate 201.

In step 1900, one or more portions of layer 1802 other than fillerportion 1803 are removed. The removal step also removes some portions oflayer 1702 such that only portions 1702A, 1702B, 1702C, and 1702D areremaining in the fabricated structure. For example, a portion of layer1702 that overlies layer 1502 is removed in this step. The removalprocess stops at layer 1502. Chemical Mechanical Planarization (CMP) isan example removal method that can be used to remove a portion of layer1802.

With reference to FIG. 20, this figure depicts a block diagram ofanother example step in the second example fabrication process forfabricating a superconducting C-coupler in accordance with anillustrative embodiment. Fabrication continues on the backside ofsubstrate 201.

In fabrication systems that fabricate from only one side, the wafer isturned over such that the fabrication can proceed on the frontsideagain. As can be seen in this figure, the wafer of substrate 201 hasbeen flipped to bring the frontside up, assuming the fabrication systemfabricates from the top. If the wafer was not flipped over in step 1300,then step 2000 may proceed on the frontside without the flip.

Oxide layer 502, which was protecting superconducting layer 402 isetched, e.g. using a buffered oxide etch if the material of layer 502was silicon oxide. The removal of layer 502 exposes layer 402 as shown.

With reference to FIG. 21, this figure depicts a block diagram ofanother example step in the second example fabrication process forfabricating a superconducting C-coupler in accordance with anillustrative embodiment. Fabrication continues on the frontside ofsubstrate 201.

In step 2100, one or more portions of layer 402 are removed. The removalprocess of this step masks and etches certain portions, which result inone or more etched areas 2102 and pads 206 forming from layer 402.Recall from configuration 200 (or 300) that pads 206 are used aselements of a qubit, e.g., to which a Josephson junction can be coupledor which become parts of a capacitor that drives the Josephson junction.The masking and etching process of step 2100 can be implemented using anexisting lithography system. As can be seen, capacitive coupling 204 isnow formed using top 1702A or the entirety of partial vias 1702 and apad 206 with intervening dielectric 205 of thickness “d”.

With reference to FIG. 22, this figure depicts a block diagram ofanother example step in the second example fabrication process forfabricating a superconducting C-coupler in accordance with anillustrative embodiment. Fabrication continues on the backside ofsubstrate 201.

The wafer may be flipped to perform the oxide etch. In some cases,etching the oxide from the backside may be performed without flippingthe wafer to bring the backside up.

In step 2200, one or more portions of layer 1502 are removed. Theremoval process of this step etches layer 1502—which in the describedexample is oxide, and filler 1803—which in the described example is alsooxide. The buffered oxide etching results in one or more etched areas2202 becoming exposed. The exposed areas include areas of substrate 201as well as pads 310. Walls 1702A and 1702B and area 1702D of layer 1702in each trench 1602 is etched to form extensions 304 and 306.

The etching also forms a space between walls 1702A and 1702B in deeptrenches 1602 such that the space is occupied by air filler in themanner of configuration 300. In one embodiment, the etching can bestopped such that filler 1803 is not removed to result in a hybrid ofconfigurations 200 and 300.

As can be seen, capacitive coupling 204 is now formed using top 1702A orthe entirety of partial vias 1702 and a pad 206 with interveningdielectric 205 of thickness “d”.

Various embodiments of the present invention are described herein withreference to the related drawings. Alternative embodiments can bedevised without departing from the scope of this invention. Althoughvarious connections and positional relationships (e.g., over, below,adjacent, etc.) are set forth between elements in the followingdescription and in the drawings, persons skilled in the art willrecognize that many of the positional relationships described herein areorientation-independent when the described functionality is maintainedeven though the orientation is changed. These connections and/orpositional relationships, unless specified otherwise, can be direct orindirect, and the present invention is not intended to be limiting inthis respect. Accordingly, a coupling of entities can refer to either adirect or an indirect coupling, and a positional relationship betweenentities can be a direct or indirect positional relationship. As anexample of an indirect positional relationship, references in thepresent description to forming layer “A” over layer “B” includesituations in which one or more intermediate layers (e.g., layer “C”) isbetween layer “A” and layer “B” as long as the relevant characteristicsand functionalities of layer “A” and layer “B” are not substantiallychanged by the intermediate layer(s).

The following definitions and abbreviations are to be used for theinterpretation of the claims and the specification. As used herein, theterms “comprises,” “comprising,” “includes,” “including,” “has,”“having,” “contains” or “containing,” or any other variation thereof,are intended to cover a non-exclusive inclusion. For example, acomposition, a mixture, process, method, article, or apparatus thatcomprises a list of elements is not necessarily limited to only thoseelements but can include other elements not expressly listed or inherentto such composition, mixture, process, method, article, or apparatus.

Additionally, the term “illustrative” is used herein to mean “serving asan example, instance or illustration.” Any embodiment or designdescribed herein as “illustrative” is not necessarily to be construed aspreferred or advantageous over other embodiments or designs. The terms“at least one” and “one or more” are understood to include any integernumber greater than or equal to one, i.e. one, two, three, four, etc.The terms “a plurality” are understood to include any integer numbergreater than or equal to two, i.e. two, three, four, five, etc. The term“connection” can include an indirect “connection” and a direct“connection.”

References in the specification to “one embodiment,” “an embodiment,”“an example embodiment,” etc., indicate that the embodiment describedcan include a particular feature, structure, or characteristic, butevery embodiment may or may not include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to affect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed.

The terms “about,” “substantially,” “approximately,” and variationsthereof, are intended to include the degree of error associated withmeasurement of the particular quantity based upon the equipmentavailable at the time of filing the application. For example, “about”can include a range of ±8% or 5%, or 2% of a given value.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdescribed herein.

What is claimed is:
 1. A capacitive coupling device (superconductingC-coupler) comprising: a trench through a substrate, from a backside ofthe substrate, reaching a depth in the substrate; a superconductingmaterial deposited as a via layer in the trench; a superconducting padon the frontside, the superconducting pad coupling with a quantum logiccircuit element fabricated on the frontside; and an extension couplingthe via layer to a quantum readout circuit element fabricated on thebackside.
 2. The superconducting C-coupler of claim 1, furthercomprising: a dielectric material filled, from the backside, in thespace between the surfaces of the via layer.
 3. The superconductingC-coupler of claim 2, wherein the dielectric material is Silicon oxide(SiO2).
 4. The superconducting C-coupler of claim 2, wherein thedielectric material is etched such that the dielectric material isremoved and the space is occupied by air.
 5. The superconductingC-coupler of claim 1, wherein a layer of a second superconductingmaterial is deposited on the frontside, and wherein the layer of thesecond superconducting material is masked and etched to form thesuperconducting pad on the frontside.
 6. The superconducting C-couplerof claim 5, wherein the layer of the second superconducting material isdeposited prior to forming the trench, and wherein the layer of thesecond superconducting material is protected by a sacrificial layer. 7.The superconducting C-coupler of claim 1, wherein the extension of thevia layer is electrically coupled with the quantum readout circuitelement.
 8. The superconducting C-coupler of claim 1, wherein theextension of the via layer is directly electrically coupled with thequantum readout circuit element.
 9. The superconducting C-coupler ofclaim 1, wherein the extension of the via layer is electrically coupledto a second superconducting pad on the backside, and wherein the secondsuperconducting pad couples with the quantum readout circuit element.10. The superconducting C-coupler of claim 1, wherein the quantumreadout circuit element comprises a ground-plane of a circuit, andwherein the C-coupler additionally functions as a grounding shield forother C-couplers coupling with the circuit.
 11. A method comprising:forming, in a capacitive coupling device (superconducting C-coupler), atrench through a substrate, from a backside of the substrate; depositinga superconducting material as a via layer in the trench; forming asuperconducting pad on the frontside, the superconducting pad couplingwith a quantum logic circuit element fabricated on the frontside; andforming an extension, wherein the extension couples the via layer to aquantum readout circuit element fabricated on the backside.
 12. Themethod of claim 11, further comprising: filling a dielectric material,from the backside, in the space between the surfaces of the via layer.13. The method of claim 12, wherein the dielectric material is Siliconoxide (SiO2).
 14. The method of claim 12, wherein the dielectricmaterial is etched such that the dielectric material is removed and thespace is occupied by air.
 15. The method of claim 11, furthercomprising: depositing a layer of a second superconducting material onthe frontside; and masking and etching the layer of the secondsuperconducting material to form the superconducting pad on thefrontside.
 16. The method of claim 15, further comprising: depositingthe layer of the second superconducting material prior to forming thetrench; and protecting, using a sacrificial layer, the layer of thesecond superconducting material.
 17. The method of claim 11, furthercomprising: electrically coupling the extension of the via layer withthe quantum readout circuit element.
 18. The method of claim 11, furthercomprising: directly electrically coupling the extension of the vialayer with the quantum readout circuit element.
 19. The method of claim11, further comprising: electrically coupling the extension of the vialayer to a second superconducting pad on the backside, wherein thesecond superconducting pad couples with the quantum readout circuitelement.
 20. The method of claim 11, wherein the quantum readout circuitelement comprises a ground-plane of a circuit, and wherein the C-coupleradditionally functions as a grounding shield for other C-couplerscoupling with the circuit.